1. Technical Field
The present invention relates to a emitter-switched power actuator.
More specifically, the invention relates to a power actuator of the emitter-switched type and comprising at least one high voltage bipolar transistor and a low voltage DMOS transistor connected in cascode configuration between a collector terminal of said bipolar transistor and a source terminal of said DMOS transistor and having respective control terminals.
2. Description of the Related Art
As it is well known, an emitter-switched power actuator is an electronic device able to supply a low voltage drop when conductive as well as a high operative frequency.
In particular, as schematically shown in FIG. 1A, an emitter-switched power actuator, globally indicated with 1, essentially comprises a high voltage bipolar transistor 2 and a low voltage DMOS transistor 3 connected in “cascode” configuration. In such way, the power actuator 1 has a collector terminal C, a base terminal B, a gate terminal G and a source terminal S. Such a power actuator is indicated with ESBT® and it is represented by the equivalent circuit of FIG. 1B.
Thanks to the cascode configuration of the high voltage bipolar transistor 2 and of the low voltage DMOS transistor 3, the power actuator 1 shows a low voltage drop when conductive and a high operative frequency, peculiarity which grows more as the “voltage rating” of the actuator itself increases.
It is possible to monolithically integrate a power actuator 1 of the type described, as schematically shown in FIG. 2.
In particular, the monolithically integrated power actuator 1 comprises a substrate 5, made of a first layer 5a heavily doped with a first type of dopant, in particular N, overlapped by a second layer 5b slightly doped with the first type of dopant N, commonly indicated as drift layer.
Above the substrate 5 a first buried layer 6 of the second type of dopant, in particular P, is realized, corresponding to the base terminal B of the high voltage bipolar transistor 2 of the power actuator 1.
In the first buried layer 6 a second buried layer 7 of the first type of dopant N is then realized whereon an epitaxial layer 8 is arranged always of the first type of dopant N.
A first 7a and a second well 7b of the first type of dopant N with low resistivity are realized in the epitaxial layer 8 suitable to contact the second buried layer 7.
Such second buried layer 7 and the regions 7a and 7b contain a portion 9 of the epitaxial layer 8 wherein a first 10a and a second islands 10b of the second type of dopant P are realized wherein active areas of elementary cells of the DMOS type are provided.
In particular, the islands 10a and 10b realize body regions of such elementary cells of the DMOS type, and they are overlapped by contact structures of the source S and gate G terminals.
The second buried layer 7 realizes instead a buried emitter region E of the high voltage bipolar transistor 2, whose base terminal B is realized by the first buried layer 6, contacted by means of a first 6a and a second well 6b of the second type of dopant P.
In essence, the monolithically integrated power actuator 1 has a symmetrical structure.
Finally, the monolithically integrated power actuator 1 comprises a contact layer 11, below the substrate 5, suitable to realize the collector terminal C of the high voltage bipolar transistor 2.
The first 7a and the second well 7b of the first type of dopant N not only contain the elementary cells of the DMOS type in the portion 9 of the epitaxial layer 8, but also allow to inhibit a lateral parasitic transistor realized by the conductivity alternation of the wells 6a, 7a and of the islands 10a, respectively of the wells 6, 7b and of the islands 10b. 
It should be noted that, since the low voltage DMOS transistor 3 is connected in series to the emitter of the high voltage bipolar transistor 2, it is a non-negligible series resistance which increases the voltage drop during the conduction phase of the actuator as a whole as schematically shown in FIG. 3B, where Is is the current flowing through said low voltage DMOS transistor 3.
In particular, the low voltage DMOS transistor 3 is in the ON state when the voltage VGATE of the gate terminal G is higher than a threshold voltage value Vth, as shown in FIG. 3A.
To decrease the resistance of the low voltage DMOS transistor 3 it is possible to increase the perimeter density of the channel. In such case it is however necessary to realize the power actuator 1 with a more sophisticated technology.
It is also possible to use, as DMOS transistor 3, a transistor MOS having an even lower voltage and a less resistive drain region. In such case, however, also a reduction can be obtained of the highest value of the current which can be switched by the power actuator 1.
In fact, during the turn-off of the actuator 1, all the collector current Ic of the high voltage bipolar transistor 2 is deviated on its base terminal B, as shown in FIG. 4B.
In particular, the low voltage DMOS transistor 3 is in the OFF state when the voltage VGATE of the gate terminal G is null, as shown in FIG. 4A.
As a consequence, a voltage drop is generated on an external resistance Rb connected to the base terminal B which increases in turn the voltage value of the base terminal B of the high voltage bipolar transistor 2 substantially corresponding to the drain-source voltage of the low voltage DMOS transistor 3.
If this voltage value of the base terminal B overcomes a breakdown voltage value of the drain-source junction of the low voltage DMOS transistor 3, a portion of the collector current Ic will flow again through the base-emitter junction of the high voltage bipolar transistor 2. In such case, the power actuator 1 is under inverted secondary breakdown conditions.